Sleep Cell:
You can understand what is Sleep Cell from the above figure.
The technique of using sleep Cell in a design is also called as power gating
This technique uses high Vt sleep transistors which cut off VDD from a circuit block when the block is not switching. The sleep transistor sizing is an important design parameter. This technique, also known as MTCMOS, or Multi-Threshold CMOS reduces stand-by or leakage power
Power gating uses low-leakage PMOS transistors as header switches to shut off power supplies to parts of a design in standby or sleep mode. NMOS footer switches can also be used as sleep transistors. Inserting the sleep transistors splits the chip's power network into a permanent power network connected to the power supply and a virtual power network that drives the cells and can be turned off
Power-gating parameters:
Power gate size: The power gate size must be selected to handle the amount of switching current at any given time.
Gate control slew rate: In power gating, this is an important parameter that determines the power gating efficiency. When the slew rate is large, it takes more time to switch off and switch-on the circuit and hence can affect the power gating efficiency.
Simultaneous switching capacitance: This important constraint refers to the amount of circuit that can be switched simultaneously without affecting the power network integrity.
Power gate leakage: Since power gates are made of active transistors, leakage reduction is an important consideration to maximize power savings.
Thanks®ards
Saikrishna Reddy .k
You can understand what is Sleep Cell from the above figure.
The technique of using sleep Cell in a design is also called as power gating
This technique uses high Vt sleep transistors which cut off VDD from a circuit block when the block is not switching. The sleep transistor sizing is an important design parameter. This technique, also known as MTCMOS, or Multi-Threshold CMOS reduces stand-by or leakage power
Power gating uses low-leakage PMOS transistors as header switches to shut off power supplies to parts of a design in standby or sleep mode. NMOS footer switches can also be used as sleep transistors. Inserting the sleep transistors splits the chip's power network into a permanent power network connected to the power supply and a virtual power network that drives the cells and can be turned off
Power-gating parameters:
Power gate size: The power gate size must be selected to handle the amount of switching current at any given time.
Gate control slew rate: In power gating, this is an important parameter that determines the power gating efficiency. When the slew rate is large, it takes more time to switch off and switch-on the circuit and hence can affect the power gating efficiency.
Simultaneous switching capacitance: This important constraint refers to the amount of circuit that can be switched simultaneously without affecting the power network integrity.
Power gate leakage: Since power gates are made of active transistors, leakage reduction is an important consideration to maximize power savings.
Thanks®ards
Saikrishna Reddy .k
